Research And Implementation Of Digital Calibration Technique For Sar Adc

Recently, the low power and high-accuracy successive approximation registeranglog-to-digital converter (SAR ADC) is widely used in portable digital signalprocessing devices. In nanometer CMOS process, the capacitor mismatch, comparatornoise and offset errors make analog design more difficult. Digital calibration techniquecan reduce the difficulty of analog design and shorten the design cycle, and it can alsotakes full advantage of the continued scaling down of CMOS process with binifits fromboth the power consumption and performance, which make this technology morewidely used.The main error source of SAR ADC, including sampling clock jitter, capacitormismatch, comparator offset, coupling capacitance, the circuit partially setup and thethermal noise limitation, are analysised and modeled. Then a classification of the SARADC is finished, and digital calibration techniques based on different structures of SARADC is summarized.Research of the traditional self-calibrating technique is done. And an improvementbased on an area optimizition structure is proposed. It can also cut off the feedbackcycle to the analog circuit, which lets it can work outside of the chip, and the calibrationcircuit does not need any more RAM which means it can adjust to higher workingfrequency. In a12bit100MS/s sampling rate model SAR ADC, simulation results showthat the calibrated ADC has an SNDR and SFDR performance increase from42.6dBand55.6dB to72.6dB and89.1dB respectively, increased five effective number ofbits.The DNL and INL are reduced from1.14LSB and25.6LSB to1LSB and0.78LSBrespectively.Simultaneously, a study about a perturbation-based digital calibration algorithm isaccomplished. The algorithm is able to work in the background, which can calibrationADC errors real-time. Larger tolerance of capacitance mismatch can make it work withsmaller capacitor design. In a12bit100MS/s sampling rate model SAR ADC, calibratedSNDR and SFDR improved from59.7dB and66.0dB to70.7dB and90dB respectively, nearly two equivalent effective number of bits improved. The DNL and INL are reducedfrom2.2LSB and3.5LSB to0.49LSB and0.49LSB respectively.Finally, a comprehensive comparison of different algorithms is investigated. TheASIC design process of the perturbation-based SAR ADC digital calibration algorithmis accomplished, and a low-voltage digital library which can further reduce digitalpower consumption is done based on the SMIC0.13μm CMOS process. The area ofdigital calibration circuit is1.0×0.6mm2.