Design Of A 12-bit 500KS/s Low Power ADC

As the rapid development of WSN technique,devices for environmental variable monitoring,biomedical,wearable and portable applications have been widely employed,where analogue-to-digital converters(ADCs)with low power and medium-to-high precision are necessary.Among various ADC structures,SAR ADCs featuring low power and simple structure attract much attention.Whereas,in certain applications requiring higher resolution,delta sigma ADC is the most popular structure.For low voltage and low power consumption application,a 12-bit 500KS/s ADC is presented in this thesis.The ADC is composed of 10-bit SAR ADC and 4-bit incremental sigma delta modulator including 2-bit redundancy,achieving low energy depletion and high performance simultaneously.After SAR ADC finishing 10-bit conversions,the residue voltage is processed by ISDM.In this thesis,a low energy consumption and low voltage switching scheme based on MSB-split structure is proposed.Combining with merged capacitor technique,where the bottom plates of differential capacitors are connected together to generate an equivalent third reference voltage,and LSB-down technique,where the LSB capacitor is unilateral suspended,the scheme achieves 99.7% energy saving and 75% area reduction comparing with conventional one.The incremental ?-? modulator employs time-domain integrator,avoiding a large amount of static energy consumption and obtaining entire first-order noise shaping simultaneously.Considering that comparator's offset can induce a large residue exceeding ISDM's integration range,offset calibration working in foreground is included in SAR ADC.Furthermore,asynchronous timing generation circuit is designed to ensure ADC's orderly operation.The ADC is designed and simulated based on standard TSMC 40 nm CMOS technology.Its active die area is 2708)*1908).The post-simulation results indicate that the ADC's ENOB achieves 11.4-bit at500KS/s operating from a 0.6V supply.And its SNDR and SFDR are 70.6d B and 74.9d Bc,respectively.The total power consumption is 5.0?W,and FOMw is only 3.7f J/conv.-step,meeting the design requirements.