A Design And Performance Evaluation Of DPR SoC Self-Reconfigurable System Based On Virtex5

Facing with the limitation of pure hardware-acceleration and the increasinglydemands for processing ability and resource, reconfigurable computing technology hasbecome an inevitable trend in compute-intensive and massive data processing SoCsystem. Meanwhile, the research direction of integrated chips based on FPGA has beingmoving towards super large scale, high density and low power consumption, whichmakes the FPGA-based reconfigurable system possible.The paper focuses on analyzing the state-of-the-art development and hotspot ofreconfigurable technology based on FPGA in the recent years, especially the design wayand performance evaluation for a novel dynamically partial self-reconfigurable system.Firstly, from the aspects of system architecture, interconnect communication mechanismand optimizing strategies, summaries of relevant theories are made out, and a newdesign framework in terms of softcore processor, dual-bus, coarse-grained devices andblack box is presented simultaneously. By comparing the efficiencies of specificcommunication approaches and design flows side by side, a design methodology basedon Proxy LUT and EAPR is chose. Secondly, the concept of DPR is introduced to a SoCsystem to cooperate to realize the function of self-controlling. To promote performanceof the DPR SoC system, characteristic parameters are set approximately and the calls ofAPI are improved at the same time. Besides, performance evaluation model isestablished; moreover, computational formula is also deduced in the paper. Finally,function and performance testing are given to verify the accuracy and reliability.