Design Of Coarse-grained Reconfigurable General-purpose Floating-point Processor Based On SystemC

A reconfigurable system is usually composed of a reconfigurable array and a generalpurpose processor.At runtime,the computation-intensive code blocks in the program are executed on the reconfigurable array,and the rest of the program is executed on the general-purpose processor.The reconfigurable system combines the high performance of dedicated computing and the flexibility of general computing,which is an important development direction of new computing.In the process of designing a reconfigurable system,it often involves a balance of considerations such as granularity,topology,memory system,and programming model which makes the design very complicated.In the early stage of design,designers need to find methods for evaluating system performance and exploring architecture.Using SystemC for transaction-level modeling can solve this problem.TLM is a rapid modeling method based on a high level of abstraction.When the target system is very complex,the SystemC transaction-level model can be used to verify the system at the architecture stage,speed up the simulation speed,and shorten the design cycle.This thesis designs a reconfigurable general-purpose floating-point processor(RGFP)that can be used as a reconfigurable computing node in a multi-core system to provide higher computing power support.In order to be able to perform functional verification and performance simulation of RGFP early in the design,this thesis uses SystemC to conduct transaction-level modeling of RGFP.The modeling is divided into two parts: one is to build a SoC system platform;the other is to design a reconfigurable hardware subsystem.First,the construction of the SoC system platform includes modeling of the RISC-V core,bus,interrupt controller,and peripheral adaptater.The RISC-V core in this thesis implements the RV32 IMAC instruction set.The communication between the various modules in the SoC system platform obeys the TLM2.0 specification;Secondly,in the design part of the reconfigurable hardware subsystem,a variety of floating-point arithmetic units are organized into a reconfigurable array in the form of a one-dimensional array,and a dynamic scheduling scheme based on two-level configuration information is proposed,using a dynamic scheduling method map computing tasks to reconfigurable arrays.After the modeling work is completed,two test schemes are used to test RGFP.The first is to run benchmarks on the SoC system platform(TLM model)and PULPino platform(RTL model)respectively.By comparing the simulation speed,the efficiency of SystemC transaction-level model in function verification and performance simulation is proved.The second is to run multiple computing tasks on the reconfigurable system to verify the dynamic data path reconstruction characteristics,parallel computing capabilities,and algorithm adaptability of the reconfigurable system.Finally,it is proved that the transaction-level model is hundreds or thousands of times faster than the traditional RTL model in simulation speed.The RGFP designed in this thesis has a good acceleration effect on floating-point computing tasks.