Research On Performance Optimization Of Coarse-grain Reconfigurable Array Processor

In recent years, coarse-grained reconfigurable architectures have become increasingly important alternatives for accelerating compute-intensive applications. More and more coarse-grained reconfigurable architectures have been proposed. Coarse-grained reconfigurable architectures become important due to its combination of the advantages of both ASICs and general processors. However, there are still some shortcomings in its loop control mechanism and memory accessing mechanism. It also can't solve the problem of input data dependence and RAW dependence of inter-iteration effectively. According to these problems, the research of this paper try to find out the basic approaches to solve these problems in the loop based coarse-grained reconfigurable architecture, then implementation these approaches in the LEAP coarse-grained reconfigurable processor.In this paper, we introduce the basic architecture and character of LEAP coarse-grained reconfigurable processor first. Against the problem of no support to branch instruction and break instruction, this paper propose the general approach to realize speculation implementation mechanism and condition break mechanism for the loop based coarse-grained reconfigurable architectureAccording to the feature that simple memory accessing mode can't complete complicated address computation, we design a new memory accessing mode: direct addressing mode. In this mode, computing array fulfills the address computation, then memory accessing unit complete the memory accessing. A basic method for solving the problem of input data dependence and RAW dependence of inter-iteration in array architecture is also offered in this paper. According the application requirements for floating-point calculation, the pipelined floating-point calculation components are added to the computing processing unit.In order to control the reconfigurable array by interface module independently and reduce the communication between the host and reconfigurable processor, we design and implement an interface coprocessor, it enhances the computing ability, judging ability and control ability of original interface module. We can control the reconfigurable array by this coprocessor effectively.To validate the effectiveness and excellence of architecture coarse-grained reconfigurable architecture after optimization, this paper select some typical loops of scientific computing, digital signal processing and media processing, then do the performance comparison by optimized mapping these loops to the LEAP architecture and microprocessor.