Research And Design Of Coarse-grained Reconfigurable Processor Architecture

With more and more flexible and complex embedded application，traditional GPP and ASIC cannot meet the demand of high performanceand flexibility。Reconfigurable processors attract extensive attention forhigh ratio of performance and efficiency，abundant computing resourcesand flexible interconnection.This paper models three mainstream coarse-grained reconfigurablearchitectures and two multi-grained reconfigurable architectures,classifies algorithms into five types：computing intensive type，controlintensive type，computing and control intensive type，I/O bound type，dataintensive type，and then maps different types of algorithm on differentreconfigurable architectures. Performance and adaptability analysis basedon simulation results has five parts: hardware utilization, computing time,input and output bandwidth, data arrangement and data reuse rate.Thispaper proposes a structure of reconfigurable array based on analysis resultand reconfigurable processor models, then introduces this structure fromsix part：reconfigurable cells，interconnection，memory mechanism，configuration mechanism，pipeline，control mechanism.Hardware modeling uses Verilog HDL.Model has passed simulationsuccessfully.Synthesis uses TSMC90nm process.Clock frequency is100MHz.Algorithm mapping result shows that hardware utilization ishigher than that of reconfigurable processor of same type when they havesame performance.This paper provides important theoretical basis for laterdesign of reconfigurable architectures.