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Design, Based On Dynamically Reconfigurable Dual-redundant System Reliability

Posted on:2011-11-18Degree:MasterType:Thesis
Country:ChinaCandidate:J C NanFull Text:PDF
GTID:2208360308466509Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
According to the continuity of time, faults can be divided into three types: permanent faults, intermittent faults and occasional failures. The foreign investigation suggested that the intermittent faults and occasional failures occupied 90% of the total field failures, and thus became the major source of systematic errors. Therefore, the study of systems with self-test and self-healing functions is very important and significant in fault detection and fault-tolerant field.Currently among the programmable logic device, the SRAM-based FPGA is widely used, but because of its unique structure, in space or other high-radiation environment it is vulnerable to single-particle bombardment, which could cause the upset of logic signal state and the changes of logic function, even the permanent damage to components and systems failure in severe cases. The traditional fault-tolerant design is based on triple modular redundancy or multi-modular redundancy method of voting to avoid errors, which could not fundamentally correct them, and the residual component failure will cause failure risks and waste of resources.In this paper, a design of an improved type of dual-redundant self-test & self-healing system based on the reconfiguration principles of FPGA dynamic part is introduced. This system uses the dual-modules comparing fault-tolerant mode, and be added to each module the self-detection function based on error-correcting codes. When fault occurred, the system could detect it in time and ensure system continues to run by reconstructing the free backup module and leading it into the system , at the same time the cut-off module can quickly determine by self-test whether it is faulty or not, and repair itself through dynamic reconfiguration technique if the fault is determined. The entire operation of the system will not be interrupted due to failures, and the detection and repair are also completed while the system is running.This paper mainly expounds the design of dual-redundant self-test & self-healing system based on reconstruction technique of the dynamic part and the implementation of SoC on hardware and software. Firstly the background of existing technology and the meaning of topic are described. Secondly the basic FPGA architecture and the principle of the vulnerability to radiation are introduced. Thirdly, through the analysis of the reconstruction technique on dynamic part and the fault-tolerant technology, the design of these modular of fault-tolerant, detecting and feature repairing is introduced. Finally, the overall design of the system as well as the specific implementation of each modular is systematically described, and the design is validated and analyzed through simulation and testing.
Keywords/Search Tags:Dynamic Partial Reconfiguration, Single Event Upset, Dual-redundant, Parity-check codes, SRAM-based FPGA, System on Chip
PDF Full Text Request
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