Research On Synchronous Multi-clock-domain Network-on-chip

Network on chip is a new on-chip interconnection structure. The use of network onchip as micro system of chip interconnect structures called network on chip system.Because the network itself is globally asynchronous locally synchronous, the existenceof multiple clock domains in the network on chip, between different clock domain isused in asynchronous communication. Data between different clock domainstransmission, due to the different clock frequency, it is bound to be a metastable datatransmission error problem.This paper mainly data for network on chip multi-clock domain under studysynchronization. The first clock network distribution of network on chip multi-clockdomain are analyzed in detail, the clock distribution network on chip clock domaindomain and discussed.Secondly, according to the metastable problem of clock domain data transmissionin multiple-clock-domain network on chip cross was studied. Discussed some technicaldata synchronization and circuit simulation, including two synchronizer, handshaketransmission, gray code transmission and asynchronous FIFO synchronization. Twolevels of synchronizer is most commonly used method, through a series of register chainto realize synchronization, you can eliminate most of the metastable cross clock domainin data transmission; transmission using the handshake handshake signals for datatransmission, can effectively avoid the metastable state and obtain the correct datatransmission; gray code is the binary data converted into gray data, to ensure that thedata transmission will not have the error data; asynchronous FIFO synchronizationthrough asynchronous FIFO memory storage, in two different clock domains betweendata transmission buffer, implemented in two asynchronous clock domains between fastand convenient real-time data transmission. On the above several multi-clock datasynchronization method, the simulation and comparison, analysis of the advantages anddisadvantages of several synchronization method.Once again, the need for multi-clock domain data synchronization of network onchip, a separate study asynchronous FIFO technology and circuit simulation. Study ofasynchronous FIFO structure, mainly includes the dual port memory, read write address address logic, logic, and empty full mark generation part, in order to realize the databetween two asynchronous clock buffer storage and transmission. This paper has madethe improvement to the asynchronous FIFO, presents a new asynchronous FIFOstructure, the structure has a relatively small number of logic gates, in two unrelatedclock domain for efficient data transmission.This paper focuses on the data of multi-clock synchronization are studied,especially the synchronization method for asynchronous FIFO, for asynchronous FIFOshortcomings, asynchronous FIFO structure of a logic gate number is proposedtheoretically.