Based On Cmos Technology Pipeline A / D Converter To Achieve

With the rapid development of semiconductor technology, integrated circuits has stepped into a new era of SOC. High-speed, low-power A/D converters are widely used as analog IP, especially in SOCs for communication and video processing. In this paper, we proposed a 10Bit 40MHz low-power pipelined A/D converter based on 0.18μm 3.3V CMOS mixed-mode process.Considering the tradeoff between high-speed and low-power, pipelined architecture was adopted. The whole ADC was comprised of 9 stage, 1.5Bit per stage. We also adopted dynamic comparator to mostly eliminate static power. Although such a comparator usually has a large offset, its effect on ADC can be eliminated by digital-error-correction. The design of operational amplifier is the key to implement the pipelined ADC. Stared from system-level analysis, we deduced the constraints of gain and bandwidth from ADC's specification. Some improvements has been made in the design of operational amplifier to better balance the needs of high-gain, large swing and high bandwidth.According to simulation results, our design can achieve SNR of 55.8dB when operating at 40MHz with an input frequency of 500kHz. Such results meet our requirements.