The Design And Implementation Of The FPGA Based Verification And Testing Platform Of NoC

With the growing number of IP cores integrated on a single chip, System on Chip(SoC) faces the bottlenecks of latency, power consumption and the bandwidth, Network on Chip(NoC)which can solve the problem of the communication of multicores becomes a research hot spot. In order to research the NoC better, the researchers use the simulators of software, hardware, and SW/HW to model and simulate the NoC. Among them, the SW/HW simulation method using the FPGA and PC machine is convenient and flexible, and can be better used in the correctness verification and performance evaluation of the NoC.Above all, we summarize the current development of the NoC, the research achievement and the commercial application trend. Then we summarize the common NoC testing methods, including software, hardware and SW/HW, compare and analyze the advantages and disadvantages of them. Then we introduce the division of the verification level, determination of the verification plan, common test methods and some common verification tools of general design based on FPGA. We propose a new core test method based on multicast-router with deadlock avoidance XY routing algorithm. It treats the unicast and multicast signals as the same, reduces the packet transmission delay, the repeated packets in the network, and the network load. And then a verification and test platform used to test the on-chip routers and the NoC is built. We describe the architectures and functions of every sub-module. After the verification of the verification platform, according to the given test procedures, we use the verification platform to test the on-chip routers and the communication network composed of several routers in multiple test cases for detailed test, and analyze the test result for accuracy analysis and performance evaluation. Finally, with the SW/HW methods, we develop an FPGA based testing platform using Xilinx FPGA board, detailed describe the structure and components, the function and the realization of every sub-module, and then use the testing platform to test the network with the3×3Mesh topology.