Study On Key Techniques For IP Router System-on-Chip

As the core device of the Internet, the Internet protocol (IP) router plays a veryimportant role in the Internet. With the rapid development of the Internet, the IP routeris facing serious challenges in its performance, scalability and power consumption, etc.On the other hand, with the maturity of the very large scale integrated (VLSI) circuittechnology, system on chip (SoC) provides a new solution to the electronic informationsystems, by providing higher system integration, improved system performance, andreduced power consumption. The design and implementation of the IP router SoC is acombination of the IP router technology and the SoC technology, by integrating the corefunctional modules of the IP router system into a single chip, and consequently providehigher performance and scalability.Based on the extensive analysis and research on the key problems of the IP routerSoC, some new solutions to the IP router SoC design are proposed in this paper. Theresearch mainly focuses on the IP router SoC architecture, the on-chip communicationstechniques, high performance IP address lookup architecture, and the functionalverification of the IP router SoC, etc. The proposed solutions had been validated bymodel-simulation, the software and hardware verification platforms.The major contributions of this dissertation are as follows.1. Based on the network on chip (NoC), the communication mechanism in IProuter SoC is studied. A virtual channel load-balanced routing (VCLBR) algorithm for2D-Torus networks is proposed, in which, the traffic load is distributed to the virtualchannels by adopting a random parameter. Simulation results show that compared withthe negative first for Torus networks (NF-T) algorithm, the network performance can bedramatically improved for different traffic pattern by selecting a specific value of therandom parameter respectively.2. A regular and symmetrical NoC topology, the semi-diagonal Torus (SD-Torus)network is proposed; with its topological properties and a load-balanced routingalgorithm are discussed. Simulation results show that, compared with the DMesh、DTorus and Xmesh, the SD-Torus network can achieve higher performance at the samenetwork costs.3. The parallel IP address lookup techniques are summarized and classified, and ahierarchical high performance IPv6IP address lookup architecture based on Hash andTree-bitmap is proposed. Furthermore, a parallel IP address lookup architecture based on SD-Torus networks, along with its algorithm are proposed. According to a so-called―Neighborhood Storage‖principle, the full routing information base (RIB) is separatedand mapped onto each SD-Torus node with its six neighbors, therefore to lower thecommunication cost for distributed IP address lookup, decrease the storage footprint andincrease the scalability of the architecture.4. A massively parallel processing (MPP) IP router SoC architecture base on theSD-Torus network is proposed. The proposed architecture mainly consists of a largenumber of homogenous processing element and a scalable network on chip. The corefunction of an IP router can be accomplished by the distributed processing elementswhich are interconnected by an SD-Torus network, therefore to build a fully distributedpackets forwarding and distributed switching IP router SoC. Experimental results showthat the proposed architecture can achieve high performance and scalability.5. A general-purpose functional verification platform for IP router SoC is proposedand implemented. As a hardware and software co-verification platform, the fieldprogrammable gate array (FPGA) device is adopted to build the functional verificationhardware platform. Furthermore, by the system configuration through the software, theplatform can be reconfigured to verify different IP router SoCs. With the flexibility ofthe software and the high performance of the FPGA hardware, the functionalverification productivity is improved greatly.