Research On Verification Of Router And Testing Of Interconnection Structure Based On 2D-MESH

With the improvement of IC design methods and manufacturing technology, the size and complexity of the chip increased significantly which leading the difficulty and cost of IC verification and testing increasing. SoC based on Network-on-Chip (NoC) have become the trend of complex chip design, and 2D-Mesh topology is the most widely used in NoC. Based on the router of the 2D-Mesh, the research content in this paper is verification of NoC and testing of interconnection structure.Firstly, we introduce the common techniques of IC verification and testing, verification methodology for SystemVerilog and the platform architecture of VMM as well. Then the verification platform is design and implemented, the tasks of verification is desided according to the router as well as functional coverage points, the function of router is proved by VCS simulating to achieve a 100% functional coverage. And then, the performance of NoC is evaluated by using the verification platform, the average network delay and network throughput of the NoC with Mesh and Torus topology varied with the injection rates are obtained by simulation at different spatial distribution of network traffic.On the basis of analysing of the difficulties of NoC testing and basic testing strategy, we propose a test structure based on 2D-Mesh topology, give the test strategies of interconnection, and design the test routing algorithm which can parallel test for routers and resources by using NoC architecture. Finally, we evaluate the test cost, test time and area overhead, the results show that test power can be reduced by shortening test data packet transmission path, and the test time can be significantly reduced by parallel test.This validation platform provides a convenient for the functional verification of router and network performance analysis, and the scheme of reusing NoC as the test access mechanism minimize the hardware overhead caused by testing.