A FPGA-based Platform For System-on-chip (SoC) Test And Verification

With the rapid development of integrated circuits chain,more and more challenges of integrated circuit design are raised nowadays.SoC?System on Chip?based architecture has become the trend of integrated circuit design and the focus of industry.One observation is that,with the performance of SoC being improved,and the integration degree increasing,the design cycle of a circuirt/chip becomes much longer than before^[1].Therefore,how to reduce the design verification and test time,to reduce the new products time to the market become an important issue.On the other hand,with the increasing of the circuit complexity,the verification and test of IC chips are becoming more and more difficult.As a result,the cost of the verification and test is much higher than before.According to a report,verification and test take about 50%⁷0%of SoC chip research and development?R&D?cycle^[2].Improving the efficiency of the verification and test therefore becomes critical to reduce the circuit R&D costs.This paper mainly proposes a FPGA-based SoC test and verification system.This system is mainly used for testing the functionality and the performance of SoC,and can covere SoC test and verification,locate the Bug and the Debug all methods of debug.The interface of the SoC is flexible and more complex than before.To achieve a configurable test and verification platform,in this work,we adopt FPGA as the implementation platform.Specifically,we use FPGA to design a flexible digital interface circuit as well as the interface controller to SoC.Moreover,a software has also been implemented for analyzing and storing the test results in host PC.The system includes hardware and software,covers various IPs of SoC control and test method.In the test system,all digital registers and SRAMs can be scanned and checked to see if all registers can be accessed,and BIST and Boundary Scan Tests can also be done through JTAG port.The Device Under Test-?DUT?can be set to the specific test mode through communication interface such as SPI,ADI,Function DMA&JTAG.In the test mode,DUT will be verified by sending control signals through test equipments.And the system will acquire and analyze the data automatically by communicating among PC,FPGA&DUT.All test results will be uploaded to data base simultaneously.Since FPGA has the flexibility to change internal digital circuit,the test system can test different digital and analog IP such as USB2.0,USB3.0,MIPI,ADC,DAC,PMU and so on.In addition,FIFO and external SRAM are integrated into the test system to enhance the ability to handle the big data.This work will only focus on IO interface between PC and FPGA.