Design And Implementation Of DPA-resistant Chip Based On LBDL Logic

With the rapid development of information technology, the security chip hasapplication in our life more diffusely. But the emergence of a variety of Side-ChannelAttacks techniques poses a serious threat on the security chip. Differential PowerAnalysis (DPA) attack is one of the most powerful side-channel analysis techniques. Insuch a technique, the power consumption of a cryptographic chip is analyzed to revealthe secret key that is used inside the device. With the development of DPA techniques,researchers began to think about how to use the DPA-resistant standard cells combinedwith other related technologies to implement the security chip.Based on lucubrating the DPA protection technologies and existing dynamicdifferential logic, a novel semi-custom design flow is proposed. According to the flow,a DES security chip based on LBDL Logic (LUT Based Differential Logic) isimplemented. The simulation results show that the DPA-resistant ability of the chip isgreatly improved, proving that the proposed semi-custom design flow has good practicalvalue. The main works and innovations of this thesis are as follows:Firstly, this thesis analyzed three typical dynamic differential logic SABL (SenseAmplifier Based Logic), WDDL (Wave Dynamic the Differential logic) and LBDL.Experiments show that the LBDL Logic can effectively solve the flip time correlationissue between the input signal and output signal, and it can completely achieve theconstant characteristic of power consumption.Secondly, a novel semi-custom design flow supporting differential routing isproposeed. This semi-custom design flow improved the traditional semi-custom designflow, and automatically replaces the netlist and layout information from single-ended todouble-ended. The proposed flow can support the differential routing, and with largedegree of automation. The timing analysis method that corresponds to the flow is basedon static timing analysis method, which replaces the delay information of static logiccell library by corresponding delay information of dynamic differential logic cell library.Moreover, the static timing analysis problems in the early stage and after differentialrouting of the design flow are properly solved.Finally, based on the proposed semi-custom design method, this thesisimplemented a DPA-resistant DES (Data Encryption Standard) chip. The differentialrouting flow and timing analysis method were verified. Moreover, a DES cryptographicalgorithm chip with the same processes and structure based on the traditional staticCMOS logic cell is designed. The experimental results demonstrate that the NED(Normalized Energy Deviation) of the DPA-resistant chip based on LBDL is much lessthan the NED of the DPA-resistant chip based on the traditional static CMOS logic cell,so the former can counteract DPA attacks much effectively.