Study Of Information Security Chip Defensive Attack

Security chip is the essential infrastructure of the information security applications that are extremely important for national defense, economy and social lives. With the development of SoC technology, a security chip can be designed to be a functional embedded system with complex hardware and software structure. However, intended attacks have been challenges to the security of embedded system, so the attack-resistant techniques and design methodologies are required. In this paper, we analyze the typical architecture, strategy and technological requirements in a attack-resistant embedded system and indicate that the countermeasures against side-channel attacks have become the critical techniques to establish a secure embedded system. Among side-channel attacks, power analysis attacks are well known and hold the biggest threat; therefore this paper mainly focuses on the system level, algorithm level and circuit level countermeasures against power analysis attacks.In this paper, the basic principle of power analysis attacks is studied, and then the power trace analysis method and its countermeasures are presented. The timing randomization scheme is investigated as a system level countermeasure, and a theoretical model is established to discover the mechanism of it. Base on this model, we compare and analyze several different probability distributions of time delay; and the optimized distributions are obtained. In addition, the multiple clocks technique is introduced into the timing randomization mechanism to avoid total power analysis. For the convenience of system integration, we propose a side-channel attack resistant unit to perform timing randomization in SoC.As for public key cryptosystem (RSA, ECC), we present three algorithms against power analysis attacks, RDE, MRDE and MRRE. All these algorithms can highly improve the security of the cryptosystem, whereas involve low performance penalty and small memory cost. The RDE and MRDE algorithm employ the method of random delayed computing, and MRDE algorithm has masking operation. The MRRE algorithm combines data masking and random recoding techniques.The attack-resistant VLSI design is also studied in this paper. We map the countermeasures against power analysis attacks into the practical chip design. A secure RSA crypto-coprocessor with multiple functions is well designed, which can be an applicable IP core for integrating in attack-resistant SoC chip. The RSA crypto-coprocessor implements two operations, modular multiplication and inverse, so it can generate the parameters for data masking automatically and perform exponentiation with random recoding exponents. The merits of this RSA crypto-coprocessor include DPA-resistant feature, improved performance and low hardware cost. The circuit design of DES crypto-coprocessor, which is resistant power analysis attacks, is also studied in this paper, and the combined scheme of disturbing circuit and complement register is proposed to generate a secure DES crypto-coprocessor with low hardware cost.