The Algorithm And Hardware Design Of Sdh Jitter Measurement Circuit

With the development of communication technology, SDH gradually became the main transmission network because of its unified speed, optical interface and frame structure. In the process of transmission, the instantaneous phase deviation between a real and the ideal digital signal caused by various of factors is called jitter. The factors which cause jitter include noises, disharmony of timing filter, inter-symbol interference, mapping and pointer adjustment.To prolong the trunk line,it's necessary to minimum the inherent jitter of system component part and jitter gain of trunk equipment so as to limit jitter accumulating. Generally, there are two aspects to evaluate transmission quality of digital signal. One is testing bit error ratio, the other is checking the quality of digital link by testing jitter. We can know the jitter characteristic, analyze jitter accumulating rule in network, find corrective actions and improve transmission quality through testing jitter. So it is absolutely necessary to measure jitter.In this dissertation we mainly study the key technology about SDH jitter measurement.The dissertation elaborates the background and significance as well as the current situation and developing direction of SDH jitter measurement technology, analyzes generating reason and impact of SDH jitter, extracts specific requirement of jitter measurement through deeply studying the ITU-T standard about jitter.According to the ITU-T specific requirement for jitter measurement, the dissertation analyzes design principle of SDH jitter measurement circuit, and proposes the design scheme of SDH jitter measurement circuit based on phase lock loop.About the main compoments of SDH jitter measurement circuit, the dissertation proposes algorithms for these compoments'design and makes algorithm-level modeling and simulation using Matlab/Simulink tool. These algorithms mainly include jitter signal source, phase lock loop and filter for jitter measurement. The algorithm-level simulation result shows that these algorithms can meet the design requirement.After the algorithm-level simulation of SDH jitter measurement circuit, the dissertation makes hardware implementation according to the algorithm, include RTL designing, RTL simulation and FPGA prototyping verification. RTL code is written in Verilog HDL and its simulation tool is Cadence NC-vrrilog. Xilinx Virtex5 is chosen as the FPGA device. The result of RTL simulation and FPGA verification shows that the design of SDH jitter measurement in this dissertation is able to complete the functions of SDH jitter generation and measurement.