Font Size: a A A

The Design Of A Fractional-N Frequency Synthesizer For IMT-2000 Standard

Posted on:2010-04-15Degree:MasterType:Thesis
Country:ChinaCandidate:Y WangFull Text:PDF
GTID:2248360275470840Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In the last decade, the rapid growth of wireless applications has led to an increasing demand of fully integrated, low-cost, low-power, and high performance transceivers. The phase-locked loop (PLL) frequency synthesizer, one of the key blocks of wireless transceivers, is used as a local oscillator for frequency translation and channel selection. Its performance indexes, such as phase noise and spur, are critical in terms of the performance and cost of a wireless transceiver.This issue intends to design a∑Δfractional-N frequency synthesizer for IMT-2000 standard. First, based on analysis and improving on literature, the linear frequency model for PLL, the reference spur caused by non-idealities of charge pump, and the implementation of capacitance multiplier are provided. Second, according to the comprehensive consideration of frequency resolution, phase noise, power consumption and area, PLL system parameters as well as circuit architecture and parameters for individual blocks are set: a complementary cross-coupled LC VCO is used, with an additional symmetric noise filtering circuit to reduce the noise from power supply and tail current source; a passive 3rd-order loop filter is used, with an area-efficient capacitance multiplier to implement on-chip large capacitance; a digital 3rd-order MASH1-1-1∑Δmodulator is used; a multi-modulus divider is used, with the divide ratio varying from 64 to 127 continuously; a simple non-dead-zone PFD is used; a current-steering charge pump is used.The result is a 4th-order charge pump PLL. It takes advantage of a∑Δmodulator to get a very fine frequency resolution and a relatively large loop bandwidth. The reference frequency is 26MHz, the frequency range is 1.88~2.03GHz, the frequency resolution is 26Hz, and the loop bandwidth is 160KHz. Circuit-level simulation with TSMC 0.18μm process and 3.3V power supply shows that, when the oscillation frequency is 2GHz, the whole PLL phase noise is -121dBc/Hz@1MHz. It is testified that this design fulfils the requirement of an IMT-2000 frequency synthesizer.
Keywords/Search Tags:PLL, frequency synthesizer, ∑Δ, fractional-N
PDF Full Text Request
Related items