Design And Implementation Of JPEG Compression System Based On FPGA

The detection of catenary-pantograph malfunction is extremely significant in current society in which the speed of train is highly accelerated. The immense data of the original malfunctioned picture makes simultaneous storage and malfunctioned picture transmission quite difficult. As a kind of picture compressing benchmark which is low in complication and high in compression ratio, JPEG has a widespread use in multimedia, network transmission and other fields. Compared with other common file formats (such as GIF, TIFF, PCX) which have the same quality, JPFG coder enjoys the highest compression ratio among present (file layouts of) static pictures.With the outstanding characteristic of flexibility and high speed in design, FPGA gradually becomes the top choice in various actual applications. Particularly, the combination with other languages like Verilog and VHDL brings great innovation to the design method of electronic system and quickens the design process of such system.This paper aims at studying and achieving a method which collect data simultaneously and can conduct compression and transmission of particular frames. By the use of programmable logic device FPGA, Video Capturing, display, compressing and transmission can be realized. This system boasts various merits. It can be designed as you wish and is high in speed.This thesis firstly provides introduction of the development about FPGA, and the relative language Verilog, the design method and procedure of development about FPGA. Then it presents relevant knowledge and design of PAL Video Capturing, which mainly involves analog video decoding control that is based on I2C bus,the introduction of video digital ITU-R BT. 601 benchmark, the attainment of video synchronous signal, video frame storage on the basis of SDRAM, VGA display command design. Subsequently, JPEG standard is described. Based on the features of malfunctioned detection, JPEG coder which can be applied in gray picture compression is then be designed. The author conducts simulation test on modules which constitute the JPEG coder. Those modules are, namely. Two-dimension DCT transform module,quantification module,Zig-zag scanning module,the DPCM of DC(direct current) encoding module,RLE(run length encoding) of AC(alternating current) encoded module,Huffman encoded module and packer module. Finally, the SRAM storage of single video frame are designed. The original pictures are compressed with the former-mentioned JPEG coder. Then the UART which only owns send capability is adopted to transmit the compressed coding to a computer, by which the received the coding is returned to the original pictures in the form of ASCII code.This thesis accomplishes, In the meanwhile, this system further verifies the correctness of gray picture JPEG coder. To some extent, this paper will be beneficial for the picture detection of catenary-pantograph malfunction and chip design of JPEG coder.