The Detection And Compensation Design Of PVT Variation For Subthreshold SRAM

Recently, the demand of mobile devices grows fast, like the mobile phone and pad, as these devices are all battery-powered, brings heat issues and shorted battery life problems. This situation has created a great challenge for energy-efficient circuit design of system on chip (SoC). As the proportion of SRAM in SoC becomes more and more increased, the power consumed by SRAM has occupied a great part in the whole system, which immediately needs a solution for reducing the power of SRAM. Traditional method is scaling the supply-voltage (VDD) and threshold-voltage (Vth), simultaneously, to accommodate both performance and power requirements, but the rapid rise of subthreshold and gate leakage has placed limits on this scaling strategy. It’s clear that new strategies are necessary to address the power concerns in high performance designs.Reducing the supply-voltage to below threshold-voltage, called subthreshold design, is a most effective solution to stringent power requirements, and has been practically demonstrated in a number of designs. Reduction of the VDD (with a fixed Vth) results in a quadratic reduction of dynamic energy at the expense of decreased performance. But for many applications, like the standby mode and some devices that the performance is secondary, including sensors and medical devices, a significant performance penalty may be tolerated without compromising the usefulness of the device. Therefore, subthreshold SkAM design is becoming an promising solution to tackle the power of memory systems.During the subthreshold region, the design of SRAM is large different from the super threshold circuit. Because the subthreshold current has an exponential relationship with the supply voltage and the threshold voltage (Vth), it leads to the delay also changes exponentially with the supply voltage and the threshold voltage consequently, which brings the extremely sensitivity to process, supply voltage and temperature variations. For example, a tiny variation of Vth caused by random doped fluctuations (RDF) would lead to a large delay or even malfunctioning and the yield of the system may then be degraded. This paper addresses the impacts of PVT on the subthreshold SRAM, and proposes a technique to detecting and compensating the PVT variations. The major work includes three regions, as follow.(1) Analyzing the impacts of PVT on super threshold circuits, and comparing the methods of variation detection and compensation.(2) Proving the challenges of subthreshold SRAM design, addressing on the most important modules, such as bitcell and sense amplifier (SA), and then proposing the design of the subthreshold SRAM in this paper.(3) To alleviate the impact of PVT variations on subthreshold SRAM, a PVT variation detection and compensation technique is proposed, based on the access time delay detecting and VDD scaling.At first, a critical delay path of subthreshold SRAM is be built to reflect the PVT variations, the delay of this critical path is be detected every cycle by the proposed detecting circuits, then according to the results of detecting, encoded circuits gives different signals for compensation. Finally, by using the low drop-out (LDO) linear regulator to scaling the supply voltage of the subthreshold SRAM and the critical path, the compensation is given. All of these circuits will be combination as an adaptive system.Experiments on different processes and temperatures are taken to test the proposed PVT detecting and compensating technique. Simulation results show that, at the normal or fast process corner, the supply voltage given by LDO is fixed to300mV, which is the lowest VDD, achieving the lowest power consumption. In contrast, the supply voltage is stabilized to375mV at slow NMOS and slow PMOS process corner (SNSP). As the temperature waves between-20to100℃, by adopting the proposed design, the average access time is decreased by64.4%and the standard deviation is reduced to17.3%, which can relief the impacts of the PVT variations on the subthreshold SRAM effectively and shorten the cycle time consequently. Meanwhile, the average energy per cycle dissipated in this design is only24.34%of the design without compensation, and the energy penalty caused by the PVT circuit is only4.38%, so that the energy efficiency can be improved significantly.