.2.4 Ghz, A Wide Loop Bandwidth Fractional Frequency Synthesizer Design

For constant envelope modulation, the direct modulation transmitter is a better choice than the commonly used mixer-based transmitter, because the mixers are eliminated and a more efficiency power amplifier can be adopted. However, the transmitting data rate is limited by the bandwidth of the frequency synthesizer.This master thesis presents the design of a wide bandwidth fractional-N frequency synthesizer with quantization noise cancellation technique for direct modulation transmitter.The loop filter design procedure based on open loop phase margin method and phase noise modeling of the PLL-based frequency synthesizer are reviewed. The△∑modulator and the quantization noise are also presented. The quantization noise folding due to the nonlinearity of phase frequency detector and charge pump (PFD/CP) is analyzed in detail. Offset PFD is adopted to make PFD/CP work in the linear region instead of improving the linearity of PFD/CP to sppress the quantization noise folding.The bandwith of fractional-N frequeny syntheiszer is narrowed to spuresss the quantization noise to meet the stringent requirement of the phase noise performance, therefore in order to enlarge the bandwidth, the quantizaition noise must be cancelled. The quantization noise cancellation technique is reviewed. The characteristic of quantization noise, which is shaped by high order△∑modulator, is analyzed. Based on the PFD/DAC hybrid structure for cancellation of quantizaiton noise of the accumulator, the modified PFD/DAC hybrid structrue is proposed to cancel the quantization noise produced by high order△∑modulator.The fully integrated LC-VCO is disscussed in detail, including the design of on-chip inductor, the choice of the varactor and the adoption of the switch-capacitor array to cover the wide output frequency range and improve the linearity of tuning gain. A 2.4GHz fully integrated LC-VCO with a 4-bit switch-capacitor array is designed. The simulated frequency range is 4.2-5.4GHz and the simulated phase noise is-119dBc/Hz at 1MHz frequency offset when the control bits are 1111. Furthermore, the closed-loop automatic frequency calibration (AFC) circuit is also designed. The control voltage is between 0.8V and 1.2V when the loop is locked.Finally, the loop of fractional-N frequency synthesizer with bandwidth of 500KHz, including modified offset PFD, arrays of charge pump, multi-mode divider, and the three order error-feedback△∑modulator, is also designed and simulated.Simulation results show that the frequency synthesizer can generate the I/Q signals with frequency range of 2.1-2.7GHz. The frequency resolution is about 16Hz. The simulated settling time is less than 8us, so the bandwidth of the frequency synthesizer is about 500 KHz. The out-of-band phase noise is lower than-110.9 dBc/Hz at 1 MHz frequency offset.