Design And Implementation Of S-Band Frequency Synthesizer Based On Δ-Σ Modulation

Delta sigma modulation frequency synthesis is an advanced technology that was developed from traditional fractional-N frequency synthesis. The delta sigma modulation is applied in PLL (Phase Lock Loop), which shapes the spur and phase noise due to fractional divider, and that will be filtered by inherent low-pass identity of PLL. Therefore we can gain frequency in high resolution, low spur and phase noise without reducing the reference or comparison frequency. Meanwhile the frequency synthesizer has relatively simple structure, so that design process and product architecture could be greatly simplified. Delta sigma frequency synthesis, the advanced and practical technology, has been widely put into application.The theory of delta sigma modulation and its mathematical model, property of noise shaping are studied and analyzed in this dissertation. The derivation of noise distribution of fractional-N PLL and system model are given. Behavior model of a frequency synthesizer based on delta sigma modulation is built in ADS (Advanced Design System), which simulates its noise shaping and reducing performance. The dissertation gives design and implementation process of a delta sigma frequency synthesizer. Fractional-N PLL LMX2485e is the core chip. Main function modules include control program and circuits, power supply, circuit filter, VCO (Voltage Controlled Oscillator) etc. Circuit filter, playing a key part in the PLL, adopts standard feedback approach in third order and active structure, which can not only amplify the output of charge pump phase detector, but also insure stability of the wild band PLL. Both restrain of fractional spur and optimization of in-band, out-band noise are achieved.The hardware system is built and implemented, which can be controlled by PC parallel port program or ARM program. The result indicates that, the frequency synthesizer covers the range from 2 GHz to 3 GHz; frequency resolution is 1 KHz; power output is 5.5 dBm; phase noise is-92.93 dBc/Hz@ 10 KHz. The system can meet design requirements.