Design And Implementation Of All Digital Phase-Locked Loop System Based On FPGA

With the constant improvement of the degree of information digitization, the information processing of electronic circuit of digital trend is becoming more and more obvious. Phase-locked loop is at the heart of most electronic circuits, its performance is crucial to the overall performance of the electronic circuit products. Traditional analog phase-locked loop performance is good, but it restrict the integrated circuit and digital form. Digital phase-locked loop can be realized through the large scale integrated circuit such as FPGA because of its unique advantages in integration and digitization, therefore the study of all-digital phase-locked loop is very meaningful.This paper analyzes the basis of all digital phase-locked loop’principle and gives All digital phase-locked loop’design ideas. According to the characteristics of the FPGA, this paper uses modular, hierarchical design method dividing ADPLL into five functional modules, and each module unit circuit design is given. Main performance index of the phase-locked loop lock is short time, small synchronous error, suitable frequency. Based on these considerations, this paper puts forward a kind of high precision and fast locked all digital phase-locked loop system. This system can automatically adjust the modulus of K, in order to solve the contradiction between the locked time and synchronization error. Using ModelSim SE6.5as its simulation environment and Verilog HDL language to complete the system design, and the main function module design process is given, simulation results show that the design is reasonable and feasible.Using Xilinx ISE as its comprehensive tool to realize the function simulation, timing simulation and programming device. Finally, the performance test is carried out on FPGA, the result meets the requirement of expectations.