The Research For Digital Phase-Locked Loop System Of Intelligent Control Module

With the flying development of science and technology, phase lock loop becomes more and more wide scope of application. Whether in communication, radar, measurement and automation control or other fields, such as signal processing, demodulation, frequency comprehensive, clock synchronization, phase-locked loop plays a pivotal role. Traditional Phase-locked loop is realized by analog circuit, its circuit structure is complex, its function exits dc zero drift and it is sensitive to voltage and temperature of environment. All digital phase locked loop inherited the digital circuit’s advantages, such as higher reliability、 smaller volume、 lower price and so on. Digital phase-locked loop also solved influence by environment temperature and had strong portability, which realizing in digital processing way is complied with the direction of the modern electronic technology. With the rapid development of the communication technology, integrated circuit technology and System on Chip (SoC) of thorough research, digital phase-locked loop will get more widely. Therefore, the application of digital phase-locked loop achieves more attention.So far as, the structure of the all digital phase-locked loop is varied, and short capture time, small synchronization error and strong anti-interference ability is a standard which can judge stand or fall of phase-locked loop system, but in digital phase-locked loop, it is incompatible between the capture of the loop time and anti-jamming performance contradiction, in order to solve this problem, several plans are proposed. This paper analyses the reason of the contradiction, and propose a structure with intelligent modulus control. Using the phase error between input and output, control the digital loop filter modulus in real-time. This way can make phase-locked loop through fast catching area, slowly catching area, then arrive synchronization and lock, at the same time, the design avoids the phase-locked loop in the capture stage appeared homonymous phase adjustment, phase jitter is reduced and the performance of the loop is improved. Because of previous phase locked loop can only apply to the case that the input signal frequency is knew, but can’t use to the unknown input frequency. Therefore in this system loop, we increase a special compare frequency latches module, which can realize the unknown input signal frequency rapid lock.This paper mainly introduced the principle and method of the phase locked loop, the design of digital phase locked loop system applies Verilog HDL, and carries on the simulation and analysis function, and uses Matlab software to analyze system frequency spectrum. The digital phase locked loop adopts digital back-end design process, and this article uses the simulation design environment for Synopsys Verilog Compiler Simulation (VCS), comprehensive tools use Design Compiler (DC), layout applies IC Compiler (ICC). The using of technology is SMIC0.18μm1P6M. The top-down design method is used as the main design way of this problem. In the design process, verification was applied in every step. This design method greatly improves the reliability of the system.