The Research On Test Pattern Generator Based On Self-feedback

With the rapid development of microelectronic technology, increasing ofintegration and complexity of integrated circuit, and the shorter channel length, thevery large integrated circuit technology can integrate above one billion of transistorsin a monolithic chip, its system’s operation frequency also can achieve above2GHz,which makes it’s more and more difficult to test integrated circuit (IC).In order to accomplish the test of system chip well and assure its reliability,Design for Testability (DFT) came into being which considers testing problem whendesigning circuit. Among DFTs, build-in-self-test (BIST) is the most widelyresearched and used technology. BIST builds the test generation, response analysis,test control unit structure and other component in the circuit under test (CUT) toachieve build-in self test of circuit, eliminating the need for expensive automatic testequipment (ATE).Test Pattern Generator (TPG) is the most critical part in BIST design, the chosenTPG decides the area of hardware and efficiency of the testing, many studies havefocused on the design of the TPG. LFSR as the most important pseudo-random testgeneration method is widely studied and applied in BIST, for its simple structure andthe smaller area of hardware. As a new BIST technology, test-patterns-applied-by-CUT (TPAC) self-test technology considers the CUT as available test resources.In the first, this thesis describes the basic theory of IC testing, introduces thebasic principles of TPAC, studies LFSR reseeding test generation techniques, andcircular self-test path (CSTP). In order to optimize the TPAC, this thesis connectspartial triggers and xor gates to form a LFSR in TPAC test structures, only obtains testpattern’s seed (L level) from the internal nodes feedback, and reseeds LFSR bycircuit-self-feedback. The experimental results on the ISCAS’85benchmark circuitsintroducing MinTest test set demonstrate the thesis can effectively reduce the testhardware overhead, and improve fault coverage.As an effective self-testing technique, the proposed method is not onlyapplicable to combinational circuits, but also to sequential circuits. This paperredesign the scan flip-flop (SFF), constructing a scan flip-flop with multiple (SFFM),SFF in SFFM could receive the response value from both its original input and theinterior feedback node. The proposed method connects partial Scan Flip-Flops withadded triggers and XOR gates to form a LFSR, and reseeds LFSR by Circuit-Self-Feedback, achieving the circuit self-test. Finally, the experimental resultson ISCAS’89benchmark circuits introducing MinTest test set demonstrate the methodis feasible and effective.