4-Bits Flash Analog-to-Digital Convertor Circuit Design In Wireless Receiver

Analog-to-Digital/Digital-to-Analog Convertor (AD/DA Convertor) connects theanalog world and the digital world, and it is the key modules of digital signalprocessing systems. Typically, the sampling rate of AD Convertor needs to meetNequist sampling theorem. However, in wireless receiver, if the ADC meets Nequisttheorem, its sampling rate has to be two times as high as the highest frequency of theRF front-end output signal. And the high sampling frequency means high cost and highpower consumption.Considering receiver output signal is generally bandpass, ADC’ssampling frequency can be no greater than the Nequist sampling rate, and based on theband width of the signals with using Under-Sampling for cost savings, reducing powerconsumption and improving spectrum effeciency. This design based on CMOStechnology is a4-bit AD Converte for wireless receiver.The ADC in this paper, which uses the Flash ADC architecture, is consisted of thesample and holdcircuit, quantizer, the bandgap reference circuit, encoder, the clockgeneration circuit and other components.Firstly, the paper introduces the analysis anddesign of the sample and hold circuit sampling capacitor, operation amplifier,bootstrap switch, quantizer which includes the reference voltage generation resistornetwork, comparators and other key modules,and in each module,there are somecommonly used technical skills presented.Secondly, the simulation is done in order toverify the design functionality of each module of the ADC, and the simulation resultsshow that the design meets the requirements.Thirdly, the layout of the ADC ispresented, which includes the entire ADC Physical map and the used layouttechniques.Finally, the system level simulation and test of the Flash ADC is done toanalyse the performance of the ADC.This design uses TSMC0.18um process,and simulation results show when theinput signal frequency is2MHz and the sampling frequency is62MHz, dynamicparameters achieves SNR of28.25dB, SFDR of34.63dB, ENOB of3.83-bit, and thestatic parameters achieves DNL <0.15LSB, INL <0.15LSB. The overall simulationresults of the ADC show that the ADC meets the wireless receiver in theunder-sampling applications.