Research And Design On Low Pin Count Interface Circuit For 3D NAND Flash

Compared with NOR Flashn3 D NAND Flash is more suitable for data storage as non-volatile memory.Recently,more and more investment in research and production about3 D NAND Flash has been made,which results in larger storage density and more mature technology,however,it has also brought huge challenges to wafer sort.On the one hand,more time is required in wafer sort,which means increased test costs.On the other hand,more complicated process makes test more difficult,which demands suitable testing methods.On engineering applications,the test time and accuracy directly determine the test cost.In order to reduce test time,combing with ONFI and referring to the idea of low pin count interface,which is widely used in integrated circuit design,this paper designed a 3D NAND Flash interface based on SPI for wafer sort,and analyzed the features of the low pin count interface design from timing perspective.Finally the conclusion was drawn: the low pin count interface has fewer pins and simple signals,but it takes 9.41 times as much time as a full-pin interface when transmitting a large amount of data because there is only one data pin.To solve this problem,this paper adopted MBIST in testing,which fundamentally reduces the dependence of data transmission on data pins.On engineering applications,testing is inseparable from automatic test equipment.Considering about the test resources of T5830 and the number of dies on one piece of wafer,the impact of the pinned time was analyzed.Finally,combining the effects of times of pinning,time consumption of 3D NAND Flash of the low pin count interface and the full pin count interface in different test mode with or without MBIST was compareed.The conclusion is made that the time consumption of the low pin count interface test using MBIST is 28.41% of the full pin count interface test without MBIST.In order to improve the accuracy of the test,this paper researched the circuit resources and randomness of the pseudo-random pattern generator in the MBIST architecture,and finally selectd the none-boundary CA with excellent randomness and reasonable numbers of circuit gates.Moreover,seed selection scheme combining 3D NAND Flash memory array structure was presented.Finally,this paper used YMTC 180 nm library to complete the digital circuit front-end design of 3D NAND Flash low pin count interface circuit,in which logic simulation and synthesis were reasonable.