Design Of A Passive Electronic Tag Demodulation And Power Circuit

NFC passive tag for its small size, low power consumption, high speed, high security features are being widely used. In accordance with ISO1443A protocol received modulated signal are100%ASK signal and have transmission rate of106kbit/s、212Kbit/s%424Kbit/s in this design NFC passive electronic tags. In order to achieve the required protocol and demodulated baseband signal accurately, this design uses a SMIC0.18-micron EEPROM technology and1.8V transistors for NFC tags demodulation circuit and power generation circuit design and analysis.Because the amplitude of the modulated signal is large, so the direct selection of the demodulation circuit is an envelope detection circuit that relatively easy to achieve. To reduce the quantization error of the demodulated signal, the design use the unity gain voltage follower, in order to stabilize the low voltage of the baseband signal. For resisting the noise of the baseband signal, the design uses a hysteretic comparator and an inverter to complete the quantized signal amplification and digital filtering finishing.NFC tag for a receiver, the additional important module is the voltage generation circuit. All the energy of NFC tag from the NFC tag antenna carrier signal, a the modulation signal have a high voltage after through the rectifier circuit and the ripple is large,so the power generation circuit decisively choice LDO circuit. In order to prevent noise interference, use the chopper modulation technique in the bandgap,it can move to the high frequency component of the noise and then filtered. To make the LDO circuit loop more stable and has sufficient signal bandwidth, between the AMP the LDO output stage uses a combination of insert buffer Miller compensation approach in this design.