Design And Implementation Of The Timing Simulation For FPGA Based On LUT

Timing analysis and timing simulation, which verify the correctness of the circuitfunctions and the normative of the circuit timing based on placement and routing, areessential parts of development environment for Field Programmable Gate Array (FPGA)supporting software and their results directly reflect whether the circuits meet the designspecifications after placement and routing.In this thesis, the basic theory of FPGA based on Look-Up-Table(LUT) and thedevelopment process of its supporting software are first introduced. For the FPGA basedon LUT, a timing analysis and a timing simulation design are proposed andimplemented. In the stage of timing analysis, the timing graph is extracted from chiparchitecture and routing data. According to the timing graph, the delay values betweenthe nodes of the circuits and the critical paths of circuits are computed. In the stage oftiming simulation, a tool called T_Simulator is designed. T_Simulator get detailinformation of the circuit after placement and routing, including connection, timing andlogic information between timing nodes of circuits, then combining of the input signals,the out signals are computed and saved in a.VCD file. The VCD file will be displayed inthe Waveform Analyzer and then the timing and logic functions of circuits is verified.The experimental results of timing analysis and timing simulation show that the programhas a good performance in execution and the correctness, the stability is also proved.