Construction Of Function Simulation Platform And Static Timing Analysis Based On FPGA Chips

Simulation is one the important steps of FPGA (Field Programmable Gate Array) design. Currently, the simulation function in domestic independently-developed FPGA supporting soft wares is implemented by buying the third party tools. There isn't independently-developed simulation software in domestic.Aiming at this condition, this thesis chooses the two simulation soft wares Gtkwave and Icarus Verilog to do the second development after analyzing and comparing the available simulation and verification soft wares. It designs and constructs an FPGA function simulation platform using the developed soft wares. With this platform, this thesis implements the function simulation of the FPGA chips and verifies the correctness of the logic functions of the circuits.In the large-scale FPGA designs, the function simulation is not enough. It can only verify the correctness of the logic functions of the FPGA circuits, but can't verify whether the timing satisfies the demands. The static timing analysis is needed.Therefore, this thesis also researches the basic principles, timing route and set up/hold time, etc. Subsequently, it analyzes detailedly the timing model picking-up principles in the bottom-up compiling strategy of the static timing analysis. With the two verification methods of static timing analysis and function simulation, it verifies the correctness of the logic functions of the circuits and the timing satisfiability, which insures that the verification is completed efficiently and reliably.