| As we pass through the deep submicron era and enter the nanometer regime, parameter variations due to manufacturing imperfections have an even greater impact on reliability and yield concerns. Corner methods produce extremely pessimistic approximations of the effects due to variations, and are completely inaccurate for interconnect, leading to over-design that reduces product profitability and competitiveness. For next generation designs, more effective manufacturing interfaces are needed to predict the performance yield and system performance during the design process. Such interfaces are essential to cope with shortening market windows and to develop more profitable products.; The primary objective of this thesis is to develop new analysis methods which address these potential problems of future high performance integrated circuit design. Hence, we first propose better performance evaluation models that offer adequate accuracy, efficiency and capacity trade-offs for use in timing verification. This thesis describes a linear-centric simulation methodology which handles time-domain analysis of the logic stages including large numbers of linear circuit elements. This analysis methodology offers significant runtime advantage while reducing the requirements for technology characterization. A prototype simulation engine is embedded in a statistical analysis framework that provides effective interface for variational circuit models. The primary purpose of the framework is to calculate statistics of circuit performance to be used in timing verification approaches, complementing static timing analysis results. |
