FPGA Timing Analysis In Test Platform And Testing Method Study Of Chip Interfaces

Testing method study of chip interfaces and establish of test platform are important partsof integrated circuit packaging testing and have important significance to the more efficient,comprehensive and simplified verification of chip interface. In the thesis, the timingconstraint and timing analysis of Altera FPGA and study on testing methods of chip interfacesare mainly investigated.In a platform system of the packaging testing, interface clock pins are connected toordinary I/O of FPGA in test platform. However, the FPGA can not identify the clock signalsautomaticly. This problem leads to data signals transmitted through FPGA can not be sampledcorrectly, which, in turn, leads to interface signals can not be sampled by external chipscorrectly. According to this critical problem, timing constraint methods of Gigabit MediaIndependent Interface (GMII), Source Synchronous Serial Media Independent Interface (S3MII)and Reduced Gigabit Media Independent Interface (RGMII) are proposed. Timing analysisresults and test results show that specific timing constraint methods proposed can ensureFPGA and external chips communicate correctly, so as to provided a stable and effecttive testplatform for interfaces.On the basis of established stable and effecttive test platform, test networks were set up,and in the view of protocol and structure of interfaces, different interfaces testing methodssuch as interface clock phase shift testing method, interface clock frequency shift testingmethod, interface clock interference testing method and interface control signals testingmethod are proposed. Study results of Ethernet communication tool, analysis results oftransmitted and received messages of tested chip displayed in testing soft and waveformdisplayed on oscilloscope show that interface testing methods raised and studied here canimprove the coverage percent of chip verification and efficiency of interface testing. It mighthave a big contribution to the verification of chip interface.