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An FPGA Implementation Of AES Algorithm For Camp Below Level Units

Posted on:2013-06-02Degree:MasterType:Thesis
Country:ChinaCandidate:Z H GuoFull Text:PDF
GTID:2248330395955458Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
The security of military information is vital to the army,and cryptographictechnique using encryption algorithm as its core is the most common and effectivemethod in information encryption.In our Second Artillery unit,there is too muchinformation and data to be protected by advanced encryption techniques.In order toprotect the military information effectively under the high tech condition,advancedencryption techniques should be widely used in battalion below level units in the army.AES(Advanced Encryption Standard) is an encryption standard that was claimed toadopt by National Institute of Standards and Technology.AES algorithm has manyadvantages in realization,such as fast,flexible,has no need for the structure ofprocessor and so on. All of these advantages make realizing AES algorithm withFPGA a good choice.At this background,this paper propose an FPGA implementationof AES algorithm which is suited for battalion below level units.The main work done in this paper is following:1.This text introduces the developing tools,language and chip that has beenselected in realizing AES algorithm based on FPGA,then the encryption procedure ofAES is introduced.According to the structural characteristics of AES algorithm,thistext particularly introduces the whole diagram of the realization of AES algorithm.2. Computers and other devices in battalion below level units are not advancedenough,but its security requirements are very stringent.Its cost and speed also hascertain request.Considering these characteristics,this paper designs a mixed pipelinestructure of inside and outside to implement the AES algorithm with a higher speed andparallel. This paper optimizes SubByte with lookup method and optimizes keyexpansion operation to achieve the goal of simplifying round functionoperation.Encryption module and decryption module are designed independently,sothey can share resources and run at the same time.3. Coding the design and testing it in MODELSIM,we receive the results finally.Then we analyse and compare the results with encryption techniques used in battalionbelow level units and other similar designs.It helps to reduce the area of hardware andincrease the speed of encryption and decryption.And it will be better suited to be usedin battalion below level units....
Keywords/Search Tags:AES, encryption algorithm, key expansion, pipeline, FPGA
PDF Full Text Request
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