Research And Design Of AES Algorithm Based On FPGA

With the Popularization and development of computer network,information security becomes one of the new researeh hotspots at present and attracts a lot of attention.Traditional cryptography mtheod by software algorithm can not meet people's need on efficiency and security in information system. Hardware cryptographic system based on hardware equipment has become an important part of seucre network platform. At the background of this development,this dissertation makes a complete research on hardware cryptographic system.With the analysis and concrete example on hardware cryptographic system,several plans are put forward to improve the performance of security,efficiency.On the basis of reseaching the AES algorithm's principium,the dissertation proposes a new AES algorithm's optimization strategy:combining the AES algorithm itself and the characteristics of FPGA and using Galois field ,linear algebra and matrix theory ,optimizes SubByte, Mixcolumn and key expand operation with look-up method , achieves the goal of simplifying operation and sharing resources in hardware design's the encryption/decryption process comparing to the exiting structures, design a improved structure(the mixed pipeline structure of inside and outside)to implement the AES algorithm with a higher speed and parallel .The dissertation uses EDA methodology to design encryption /decryption module,key expansion module of the AES under a mixed pipeline structure,and use VHDL language to describe and complete the optimized design and implementation of the AES algorithm encryption and ecryption system in an FPGA chip Coded and synthesized the design with the QuartusII development tool,simulate the the AES algorithm encryption and ecryption system in function and timing , and gave the simulated the tested results of all sub-modules and overall system .Compared with other designs,this system works at a balance in a the speed and area,The performance is superior.