Improved Research FPGA AES Encryption Algorithm

AES(Advanced Encryption Standard) in May26,2002became effective standard.AES algorithm research has became a hot topic at home and abroad, and the algorithmhas been widely applied in the field of information security. Since the algorithm ofAES key expansion part is open, so the key is between the wheel can be derived fromeach other, the AES algorithm designed for this security risk by generatingpseudo-random number. Logistic mapping a certain length, after quantization are usedas a key to improve the security of the AES algorithm. AES is a block ciphertechnology, algorithm contains a large number of linear and nonlinear operation, usingFPGA to implement AES with fast, flexible, short development cycle and so on. So thedesign is implemented on an FPGA development platform.In the modified AES algorithm design process, the first to complete the simulationimproved AES encryption algorithm using matlab to verify the feasibility of the newencryption algorithm. FPGA Verilog HDL coding and then the overall program design,and implementation of each module. Including the serial port receive and transmitmodule, string and conversion module, a control module, a pseudo-random sequencegenerator module, encryption module, decryption module and string conversionmodule and so on.