Research On FPGA-based RFID Data Encryption Algorithm

With the development of the internet of things, as the key technology, RFID is of great concern. China carried out a large number of projects about RFID, and is preceded only by America in the world since2009. RFID is easy to use and compared to traditional IC card or barcode techniche, RFID have great advantages. However the security problem is the bottleneck that restricts its development. The incident of successfuly crack of NXP’s Mifare Class chip (often referred to as M1chip), caused great concern of the security of the RFID chip in the world. The M1chip is widely used in the world, and is also widely used in many systems in China. Many systems such as the access control system or the card payment system faces great risk. In order to solve the security issue of RFID, this paper researched about the implementation of encryption and decryption algorithm which can be used in the RFID chip. In order to meet the safety and high performance requiements in the RFID chip, this paper studied the efficient implementiton of the algorithm to provide high throughput with low area and low power consumption.This paper describes the current security situation of the RFID system and the safety and mathematical properties of AES encryption algorithm, and researches on the structure of the AES algorithm, the methods of improving the performance and the way to reduece the power consumption. The work of this paper includes these aspects below:1. In the hardware implementation aspect, a pipelined encryption and decryption structure was designed for high performance based on the research of the AES algorithm.2. In the performance aspect, the hardware circuit is optimized and the critical path is processed by pipeline to improve the throughput.3. The clock gating technich was also used in the implementation of the security chip to reduce the power consumption. And based on the similarity of encryption and decryption, many resouses was reused to reduce area.4. A data width compatible MCU interface was designed, and with the expanded interface, the AES IP could be easily used in embed systems.5. The UVM Verification Methodology is adopted to build the automated verification platform.The designed hardware of the AES algorithm and the extended interface is simulated and implemented on FPGA. And at the end of this paper, the research is summarized. It makes out the points of innovation and the main results of the research, it also points out the further researches.