Research On Implementation Of High Performance AES_CBC Algorithm Based On The Technology Of Single-Chip FPGA

Algorithm Rijndael has been selected as the Advanced Encryption Standard (AES) by NIST in 2000 October. The AES_CBC will be used to replace the DES_CBC and 3DES_CBC in IPSec.The Encryption is the key technology of secure network. The encryption need to be done to protect the information on the public network from interception and monitor. The high speed AES_CBC encryptor/decryptor core with no negative affect on the performace of network is very important for high speed communication device such as high speed secure router and secure gateway.The fastest speed of Encryption/ Decryption based on FPGA implementations is 700 Mbits/sec/ 400 Mbits/sec as far as we know. The fastest software implementations of AES_CBC are made by Helger Lipmaa. The peak Encryption/ Decryption speed of a 3.06 GHz Pentium IV processor is 1.4Gbits/sec. The test made by the abroad expert shows that AES_CBC implemented by sofrware only get the speed of 600 Mbps which is the lowest throughput requirement of a router with double high performance 64 MIPS NP.In this paper, we first make the comparison and analysis of several hardware and software implementations of AES_CBC. It shows that the implementation of AES_CBC algorithm based on the technology of FPGA can get the character of both the flexibility of software and the high speed of ASIC. Then a new implementation of AES_CBC for high speed encryption and decryption in secure router is proposed in this paper. In this new solution, encryption and decryption work as parallel tasks and sub_key online is introduced. It is based on double queues which allow the encryption and decryption of AES_CBC cipher to work on the same high speed. In the implementation, the encryptor/decryptor includes a non-pipelined encryption datapath with an on-the-fly key schedule datapath.This paper also addresses the verification of my AES_CBC implementation to show its validity, as well as its performace. The single-chip encryption core can run at 100 MHz resulting in a throughput of 1.16 Gbits/sec on stratix EP1S20F484C5 FPGA divers, the descryption single-chip core can run at 80 MHz resulting in a throughput of 900Mbits/sec on stratix EP1S20F484C5. The muti-chip core can run at 80 MHz resulting in throughput of6.4Gbits/sec. This is the fastest single-chip FPGA AESCBC encryptor /decryptor core reported to date.At the present time, only simulation approach is used to verify the correctness of my AES_CBC encryptor /decryptor because of the limitations of work environment. Futhermore verification can be made through dowdloading the code to a cmos chip. Future work for IPSec will focus on the FPGA to achieve hardware implementation. In conclusion, more efforts need to be made to adapt the development of high performance router.