A High-speed And Small-area Implementation Of AES Algorithm Based On FPGA

AES is one of block cipher algorithm. Because of the high safety, AES has been the research hotspot since it was born. And the realization of the algorithm has many advantages,such as designing easily, processing fast, data parallel processing, making a change of the length of the data block, having no special need to the processor struction, having no complex operation and so on. All of these make it a good choice to realize the AES algorithm based on FPGA. Howere, how to design AES with FPGA to make it operate faster, use smaller resource and reduce power is still a problem.Based on the aims above, this paper presents a new architecture model to implement AES algorithm based on FPGA. In this model, the part of key expansion is implemented by microprocessor without FPGA, and the secret key storage is shared by both encryption and decryption module. To the design of encryption and decryption, the basic structure is used to save FPGA resource, the techniques of data parallel processing, looking up table and so on are used to speed up the operation. Thus it not only meets the demand of Real-time,and saves a lot of FPGA resource , reduces power waste. This model can provide important reference for the implementation of AES algorithm in small area FPGA at low voltage. Because the data length of AES is 128bit at least, so the circuit of AES is difficult to connect the out equipment directly. In order to reslove the problem, the 8bit data port is successfully designed. The data of encryption or decryption or key-expansion is teansmitted by singlechip. Finally the design model is realized by hardware, passed the correlative tests. The result datas of encryption and decryption are showed by the serial port debugger.