The Research Of Reconfiguration For Low-power Cache In Embedded System

As CMOS technology continues to scale down, the energy consumption ofmicroprocessors has become a major constraint in the state-of-art embeddedmicroprocessors design. Caches technology is based on the locality principle ofthe program, and it has been playing a key role in bridging the performance gapbetween low-speed main memory and high-speed microprocessors. It is a keytechnology for optimizing the performance of computer systems. Several studieshave shown that on-chip cache memories account for about half of the totalenergy in modern microprocessors. The research of high performance and lowpower cache has significant means for the embedded system.Reconfigurable cache technology is based on the principle of rationalallocation of resources that has been a major concern among the low powerresearch. It has a set of adjustable configurations, and tuning the cacheconfiguration depending on the requirement of applications to make the best useof resources. Self-tuning algorithm for reconfigurable cache can monitor cache behavior, performance and dynamically modify its configurations according tothe requirement of running program, and minimize the energy consumption andperformance loss. Two self-tuning algorithms for reconfigurable cache ofembedded system are presented, which uses state machine to identify the changeof program locality feature and make a decision to adjust cache’s size andassociativity in each phase.The first algorithm use program branch rate to monitor the change ofprogram and to seize the opportunities of reconfiguration. Then the algorithmaccording to the cache miss rate, and make use of the optimizedconfigurations-searching method to find the best configuration for runningprogram within the shortest possible time. This algorithm was easier toimplement than second one. The experimental simulation shows that comparedwith the conventional4-way cache, the algorithm effectively lowers cachepower up to48percent and by an average of39percent.The second algorithm improves the first one. It takes the program workingset signature replace of the branch rate that makes monitoring of the changes ofthe program more accurate. It effectively reduces redundant reconfiguring and lost opportunities of reconfiguring. The experimental simulation shows that thealgorithm effectively lowers cache power up to68percent and by an average of64percent, and reduces rate up to96percent on cache miss rate and by anaverage of3percent on run cycles than an conventional4-way cache.