Design Of Power Configurable Pipelined ADC

The Internet of Things technology, represented by CMOS image acquisition system, has attracted the attention of numerous domestic and foreign researchers in recent years. It is a great demand to maintain a high linearity and energy efficiency at different data update rate for image acquisition devices. The key to reach this requirement is to make the dissipation of ADC system configured and optimize the power consumption at different data update rate. In addition, the reducing supply voltage of chips has brought much challenge to the design of analog circuits including ADCs. Therefore, the ADC in chip system with low supply voltage, high swing and high linearity is becoming the great difficulty and emphasis to chip design.The pipelined ADC mainly optimizes the aspects in the signal swing, linearity and power consumption. The innovation and improvement of this paper are as follows:1) This ADC uses bootstrapped switch to improve the linearity of sample and hold circuit. The ADC apply two-stage fully differential operation amplifier in the sample-hold and multifunction-gain stages to improve the swing of signal. There is a switch capacitor common mode feedback circuit in both the two stages of amplifier to reduce power consumption of the circuit.2) 2.5 bit per stage structure has been adopted in this system to improve the nonlinear due to capacitor mismatch; Current configurable circuit controlled by serial signal bit is added in bias circuit in order to optimize the linearity deterioration of operating amplifier due to its operating point change.The pipelined ADC uses GSMC 0.18 um RF CMOS process, the area of layout is about 1.982 mm. The circuit and layout has been finished, as the simulation results shows, SNR and linearity have both reached more than 10 bit.