Research On Self-tuning Low-energy Algorithm For Way-Predicting And Reconfigurable Cache

One of the uncompromising requirements from embedded system is high performance and low power. As the performance bridge between CPU and DRAM, Cache is playing an important role on optimizing the performance of computer, but it consumes significant energy of CPU. Reducing the energy dissipation of Cache has significant means for saving the computer system energy consumption.Although way predicting is an efficient method for reducing the power consumption, system performance will be degraded when predicting accuracy is low. A Dynamic Self-Tuning cache architecture based on Way-Predicting (DSTWP) is presented. Depending on the values of the predicting accuracy and the Spatial & Temporal Locality of the running program, selectively switch the predictor for eliminating the negative factors of the predicting scheme. The experiments show the architecture can decrease energy consumption without significantly hindering performance.As the running programs have different requirements for Cache, with the help of the self-tuning algorithm, reconfigurable cache can dynamically modify its configurations based on the requirements, and minimize the energy consumption and performance loss. Based on the LRU, a novel Way Reconfigurable Cache algorithm (LRU-WRC) is presented in this paper. Depending on the results of the LRU, the algorithm disables the Cache line which has the worst Spatial & Temporal Locality. With a highly accurate reconfiguration, the algorithm can reduce the energy consumption without degrade the system performance distinctly.Both of the DSTWP and LRU-WRC are algorithms for degrading energy consumption. With their similarities, presents a new algorithm named WPRC (Way-Predict Reconfigurable Cache) combines DSTWP and LRU-WRC together. WPRC can adjust two algorithms working in the same system. The results show that WPRC provides the better power savings while meet the performance's need.