Research On Self-tuning Low-energy Algorithm For Reconfigurable Cache And CPU

In the last decade, limiting computer energy consumption has become an important goal in computer design, largely due to grow use of portable and embedded computers with limited battery capacities. This paper concerns how to reduce processor core and cache's energy consumption, since the processor core and cache consume much of a computer's energy.Reconfigurable cache has a set of adjustable configuration, and the self-tuning algorithm for reconfigurable cache can monitor cache behavior, performance and dynamically modify its configurations based on the requirement of running program, and minimize the energy consumption and performance loss. A phase-based self-tuning algorithm(PBSTA) for reconfigurable cache is presented, which uses state machine based on instruction working set signature for identify the change in program and making a decision to adjust cache's size, and uses state machine for governing cache and determining how to adjust cache's size in each phase. In contrast with previous works, the algorithm seeks not only to effectively lower the cache's energy consumption, but also reduce the performance loss due to unnecessary reconfiguraitions.Dynamic voltage scaling is an effective way to reduce processor energy consumption through changing the processor's supply voltage and clock frequency at runtime. However, the processor energy savings comes at the cost of degraded performance because slowing the voltage would increase the circuit delay. So, it needs an algorithm to decide when and how to scaling in order to saving the processor energy while meet the performance's need. A phase-based voltage scaling algorithm(PBVSA) is presented, which uses state machine for identify the change in program and making a decision to change the processor's supply voltage and clock frequency, and sets processor's voltage and clock frequency by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time(β) in each phase. The results show PBVSA effectively saves the processor energy while meet the performance's need.Although PBSTA and PBVSA could effectively lower the cache or processor's energy consumption, their combined effect on power consumption might not be simply a linear combination of the two optimal solutions. An algorithm (CVPBSTA) is presented that combines PBSTA and PBVSA, which uses state machine for identify the change in program and making a decision to adjust cache's size and processor's supply voltage and clock frequency, and uses state machine for governing cache and determining cache's size and sets processor's voltage and clock frequency by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time(β). The results that CVPBSTA provides the best overall power savings while meet the performance's need.