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A6-12bit Configurable Low Power A/D Converter

Posted on:2014-11-18Degree:MasterType:Thesis
Country:ChinaCandidate:W J LiFull Text:PDF
GTID:2268330401953809Subject:Microelectronics and Solid State Electronics
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As the bridge of the real world and the digital process system, Analog-to-digital Converters (ADC) are widely used in portable sensors, embedded devices and wireless communication systems. Due to the limitation of battery capacity and the volume of equipment, the requirement of low power and compact area becomes more and more stringent in the design of ADCs. While considering the variable processed signals, it is becoming a tendency to get different resolutions from one ADC.Based on TSMC0.18μm1P6M CMOS process, an embedded, low power,6to12bit configurable1MSPS analog-to-digital converter is implemented. The converter has a SHA-less cyclic pipelined structure, with area of only0.2mm2. There are9multiplexed single ended channels or8multiplexed differential ended inputs. One active model and three power saving models are used for the consideration of low power design. Besides, in the active model, the bias current will work in7different conditions with the change of clock frequency. At last, when the converter works at12b resolution and1MHz sampling frequency, the simulation result of SNDR is73.6dB, SFDR87.29dB, SNR74.1dB with a116.2KHz sine wave input signal, that is11.93efficient number of bit. The power now it consumes is only2.9mW.
Keywords/Search Tags:Cyclic pipeline, ADC, Configurable resolution, Configurable powerCMOS
PDF Full Text Request
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