The Td-scdma Lte Baseband Chip Verification System Signal Integrity

As the next generation communication technology, LTE, taking the advantage of technology and cost has been accepted widely, it means that the LTE baseband chips have to be researched and the corresponding verification set up. This paper is analyzing and studying the signal integrity about the high-speed PCB, basing on the design of TD-LTE baseband chip verification platform.This article briefly describes the structure of the TD-LTE baseband chip verification system, and analyses the signal integrity requirements of the key modules. It also elaborates the basic principles used in signal integrity in high-speed PCB design, including the transmission line theory, skin effect, signal reflections and signal crosstalk. Combined with the actual demand, a variety of simulation models and their respective scope of application are introduced, and the IBIS model is selected to process the behavior level simulation. Finally, taking verification platform specific signal for example to make simulation analysis and to gradually improve the design, the author completes the optimization of system structure successfully,and the result meet the requirements of the verification platform for signal integrity, and the work of LTE baseband chip functional verification is completed.Innovation and the results of the work of this paper are as follows:1) According to the baseband chip design architecture, the author participated in the design of the baseband chip verification platform, chip verification and debugging work.2) The simulation of the baseband chip FPGA, SDRAM memory, standard high-speed connection between single-ended signal reflections, crosstalk is completed. Besides, the author also formulated a detailed PCB design constraint rules simulation according to the simulation results, and provided a practical method for high-speed PCB design.3) Through the baseband chip external memory interface topology simulation, we obtained that shared high-speed and low-speed storage device, part of the bus program has some limitations conclusion, poor compatibility with a higher operating speed of the memory module, a baseband the design of the chip, the follow-up version of the reference views.4) The high-speed differential serial signal simulation study is completed, and the author through analyses simulation results (eye diagrams) to gradually optimize design, and achieves1GHz good differential signal transmission, which has practical significance for higher speed serial differential signaling.