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Design And Implementation Of A High-speed High-resolution Time-interleaved Analog-to-digital Converter

Posted on:2014-05-08Degree:MasterType:Thesis
Country:ChinaCandidate:S B JiaoFull Text:PDF
GTID:2268330401967726Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
High-speed and high-resolution analog-to-digital converter (ADC) is a keycomponent for many modern electronic systems, such as wireless communication,radars, advanced imaging, instrumentation, and medical instruments. Based on thecurrent IC process conditions, it is difficult to achieve the performance of high-speedand high-resolution with the monolithic ADC. Time-Interleaved ADC is applied as aneffective way to implement the conversion rate of the analog-to-digital converter.Unfortunately, offset, gain, timing and bandwidth mismatches between theTime-Interleaved ADC channels produce undesired spectral components which make itdifficult to achieve high resolution. This paper focuses on the mismatches existing in theTime-Interleaved ADC.Firstly, this paper presents an overview of the operation of Time-Interleaved ADCand of the mismatches which occur in the sampling process. It reviews previousdomestic and documents about Time-Interleaved ADC and outlines the contributions ofthis thesis.Secondly, a four-channel12bit400MSPS of the Time-Interleaved ADC hardwarewas designed. The key technologies include the analog-to-digital converter, analogfront-end circuit, high-precision multi-phase clock generator and high speed systempower adaptor. Especially, parts of the circuits were simulated and implemented.Thirdly, this thesis deals with the identification and compensation of offset, gain,timing and bandwidth mismatches in Time-Interleaved ADC. The digital backgroundcalibration algorithms were also simulated with matlab tools. The circuits of the digitalbackground calibration algorithms were designed and simulated.Finally, the Time-Interleaved ADC test and verification platform were developed.The test scheme and the ADC measurement results were shown. The Time-InterleavedADC dynamic performance is shown with and without the digital backgroundcalibration. The Time-Interleaved ADC dynamic performance is obviously improved bythe test. A performance summary and a comparison with other published works arepresented.
Keywords/Search Tags:Time-Interleaved ADC, timing mismatch, bandwidth mismatch, digitalcalibration algorithm
PDF Full Text Request
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