A High-Speed Pipelined DEM Encoder And LVDS Receiver Design

High-speed, high-resolution CMOS D/A converter, which is a key component ofmodern mobile communications, broadband imaging radar systems and modernwireless networks, plays a very important role. Based on the project-design of a14bit-1Gsps DEM Digital-to Analog Converter, a1Gsps dynamic element matching(DEM) encoder and2Gbps low-voltage differential signaling(LVDS) receiver arerealized in this dissertation, using SMIC0.18um1P6M standard CMOS process.This DEM encoder, which is used as thermometer decoding circuit in the DAC, isdesigned in standard ASIC flow. The design procedure includes algorithm realization,logic synthesis, physic design and timing analysis; The LVDS receiver, which isused as the digital input interface of the DAC, is realized in analog circuit designapproach. Its structure is composed of pre-amplifier, hysteresis comparator andshaping buffer module.Based on PrimeTime and Modelsim tools, the DEM encoder is verified afterbeing designed. The results indicate that it exhibits good performance under1GHzclock frequency, completely satisfying the design specifications; Based on CadenceSpectre simulator, two simulations to the designed LVDS receiver are done beforeand after its layout, respectively. The simulation results show that the implementedLVDS receiver is IEEE STD1596.3compliant. When it operates under the conditionof2.5Gbps input data rate and0.1pF load capacitance, the output waves of thereceiver have nearly ideal occupancy(50%) and abrupt transition edges. Therefore,the LVDS receiver can work stably and reliably, completely satisfying therequirement of the project.