Fractional-N PLL Frequency Synthesis Based On Σ△ Modulation

With the development of wireless communication system and the enhancement of frequency that micro processor is operated on,the requirement of frequency synthesizer is increasingly high.At present,the PLL(Phase Locked Loop) frequency synthesizer is extremely popular.In the research and the practice of engineering,the PLL frequency synthesizer is developing all the time.Fraction-N frequency synthesizer is invented in order to solve the conflict between the tracing time and the frequency resolution.To reduce the serious phase noise in fraction-N divider, the technique ofΣ△modulation is used in PLL frequency synthesizer,and the PLL fraction-N frequency synthesizer based onΣ△modulation appears.In this paper,the basic structure of PLL frequency synthesizer is researched,then it is introduced that what is the modules' characteristic and how they can influence the phase noise.This paper also introduces the implement of fraction-N frequency synthesizer and the how to deal with its phase noise.This paper studies the basic structure ofΣ△modulator and its noise characteristic,and then builds up the analyze model ofΣ△modulator in Matlab.In such circumstance,the noise shaping characteristic in researched and it is observed that how could the different over sampling rates influence the SNR(Signal Noise Ratio).In this paper,aΣ△modulator IP core for PLL fraction-N frequency synthesizer is designed by employing design method of all digital.In the technique of TSMC 0.18μm CMOS,logic synthesis and layout design of the circuit are finished,and the clock frequency is 50MHz,layout area is 0.074 mm~2.Through the verification,the circuit fulfils the requirement of design specification completely.The characteristic of noise shaping is rather nice and the phase noise is low.