A Fractional-N Phase-locked Loop With Spur And Noise Suppressing And Compensating

With the development of VLSI technology, the requirements of the clock signal are getting higher. Some of the factors, such as resolution, phase noise and switching time domain the performance of clock synthesizer. Fractional-N Phase locked loop is the fundamental structure of achieving high resolution and switching time, but it will cause the spur which will decrease the noise performance of PLL. Suppressing and compensating the spur come into the challenges.This paper will put our main attentions on how to optimize the noise performance of fractional-N PLL system. By analyzing the noise and spur sources, the methods of supperssing and compensating technologies will be discussed. In the design, by reusing functional blocks, we will research the possibilities of decreasing the output jitters of fractional-N PLL system without increasing the power dissipations.The main contributions of this paper are as follows.(1)Studying the fundamental structures of fractional-N PLL, analyzing the noise sources and their mechanisms, build the noise model of fractional-N PLL. Corresponding methods of suppression and compensation technologies of spur noise have been proposed. Researching effects of the loop bandwidth on systematic noise performance, the principles and advantages of self-biased adaptive bandwidth technology is considered. A structure which can decrease the capacitor is presented. The simulation results under 40 nm and 65 nm prove the strong universality of our PLL.(2)A strong universality, self-adaptive high bandwidth, low-jitters fractional-N PLL in 40 nm process is proposed. A novel charge pump is considered to improve the linearity, by inputting the shaped least bit dithering to the ΔΣ modulator, the spur noise lead by it will be decreased. A noise compensation technology based on ΔΣ digital-to-analog converter is researched, by using the dynamic elements matching technology, the performance of DAC will get better. A novel two-stage divider is proposed to decrease the power dissipations.(3)In order to accelerate the speed of simulation, we proposed a RTL-transistor level model based on Verilog-Spectra which can largely decrease the simulation time.The layout of this PLL is built in 40 nm CMOS process, we successfully verifies the function of our fractional-N PLL design in Hspice models. The phase-noise performance of this PLL will achieve-130 d Bc/Hz@3MHz, the maximum VCO output is up to 3.2GHz, the lowest resolution is 0.048 Hz, the area of core die is 0.07mm2...