A Kind Of Application In The Soc Chip With Target Detection Precision Of Phase-locked Loop Design And Research

With the development of SoC (System on a Chip) technology, phase-locked loop (Phase Locked Loop, PLL), the system clock providing module, has become more and more important, since its performance imposes a major impact on the performance of the entire SoC system. With a view to SoC applications, a PLL should provide not only a desired clock with a proper range of frequency, low jitter, and a short lock time, but also a lock detecting flag indicating whether the clock is stable.In this thesis, after introduction of phase-lock technology, the charge pump phase-locked loop (charge pump PLL, CPPLL) structure is chosen for the clock generator circuit, which had been used the widely and have a good performance. Based on the principle of CPPLL, the clock generator is designed. Additionally, a lock detection module is also included with special functions according to the actual SoC requirement that guarantte the lock detector can perform correctly in any case. The PLL has been taped out as a clock unit integrated into two SoC systems, under the SMIC0.18um and the TSMC65nm technology, respectively. The measurement results for the65nm PLL have been presented.