Rapid Lock CMOS Charge Pump PLL

PLL (Phase-Locked Loop) is a synchronous feedback system. It has a wide range of application in many fields. CPPLL (Charge Pump PLL) is currently the mainstream of PLL design because of its advantages of small phase difference、low jitter, etc.Firstly, this article describes the working principle of CPPLL and the structures and working principles of its5sub-modules------phase frequency detector(PFD)、charge pump(CP)、loop filter(LF、voltage control oscillator(VCO) and divider.Secondly, after comparing different structures of these five modules, I determined the structures that I would use in this design.Thirdly, based on TSMC0.18um CMOS process, I designed the specific circuit of each module by using ADS. Improved PFD achieves small dead-zone,and it is about45ps. The mismatch of charge current and discharge current of improved CP is small, and it varies from-0.710to0.03%. And its current variation becomes much smaller, which is about1%. The center frequency of LC VCO is about2GHz. Its output frequency ranges from1.799GHz to2.567GHz. Divider module uses5TSPC-DFFs which can work quickly to cascade with each other to achieve dividing by32. The simulation result of the overall system shows that the duty cycle of output waveform is close to50%, and the PLL is almost locked at22us.Finally, under the tsmcl8rf model library, I finished the simulation of PFD and Divider by using Spectre tool. After that, I completed the layout design of them by using the Virtuoso tool, and extracted the parasitics of their layouts by using Calibre tool and post simulated them. At last, I compared the pre-simulation and post-simulation results of PFD and Divider, and analyzed them.