Based On 55 Nm 1.6 Ghz Model Cppll Frequency Synthesis Device Design

With the continual development of integrated circuit(IC) technology and increasing of IC design capability, the programmable phase locked loop with high speed, low power and low noise has become the most used IP for SOC design. Based on the HLMC55nm LP process, a high performance1.6G Hz PLL is designed. To meet the requirement of high speed counter, a pre-divider, a8bit BCD (Binary Coded Decimal) code converter and a8bit series counter are used to provider8bit high speed frequency divider. For getting the high stability of system, a wide input range phase frequency detector (PFD), a charge pump (CP) with symmetrical input and a differentially voltage controlled oscillator (VCO) with very good anti‥‥interference have been applied.The thesis has completed the specification of frequency synthesizer (FS), schematic of PFD, CP and high speed divider design, pre-simulation, layout design and post-simulation. An output range500MHz to1.6GHz, high stable and programmable FS has been designed. The double power system’s area is0. lmm2, the power dissipation is2.63mW, Jitter is12pS. And the measurement plan has been completed.